Code.No: NR/RR310201
NR/RR
SET-1
JAWAHARLAL
NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD III B.TECH I-SEM SUPPLEMENTARY
EXAMINATIONS JUNE - 2010
COMPUTER ORGANIZATION (Common to EEE, ECE, EIE & ETM)
Time:
3hours Max.Marks:80
Answer
any FIVE questions
All
questions carry equal marks
-
- -
1. (a) Distinguish between basic bus configuration and P C I configuration.
(b) Perform the arithmetic operations
35 + 40and - 35 + (- 40) with binary numbers
in singed 2’s complement representation and signed- magnitude representation.[8+8]
2. Explain the following branch instructions of a hypothetical computer:
(a) BRP X
(b) BRN X (c) BRZ X
(d) BRO X. [4+4+4+4]
3. (a) List the micro-operations required to carryout the following instructions. Assume
a simple CPU with single accumulator.
i. AND to accumulator ii. OR to accumulator iii. Jump
iv. Jump
if AC = 0.
(b) The ALU is a combinational circuit with no internal
storage. Justify this. [12+4]
4. (a) Explain the following terms:
i. Micro program
ii. Microinstruction
iii. Microprogramming
iv. Microprogramming language.
(b) Draw the diagram of micro
architecture control unit and explain. [8+8]
5. What
are the different mapping techniques
of cache memory? Describe
each technique with a suitable diagram.
[16]
6. (a) What do you mean by virtual memory?
(b) Explain the demand paging technique in detail. [8+8]
7. (a) What is the purpose
of I/O interface? Explain
the Communication link between
the processors I/O bus and peripheral devices.
(b) Describe different commands that an I/O can receive from CPU. [8+8]
8.
(a) A DMA controller transfers 16-bit words to memory using cycle
stealing. The words are assembled from a device that transmits characters at a rate of 2400 characters per second. The CPU is
fetching and executing instructions
at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
(b) What are Bus arbitration schemes? Explain.
[8+8]
*****
Code.No: NR/RR310201
NR/RR
SET-2
JAWAHARLAL
NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD III B.TECH I-SEM SUPPLEMENTARY
EXAMINATIONS JUNE - 2010
COMPUTER ORGANIZATION (Common to EEE, ECE, EIE & ETM)
Time:
3hours
Max.Marks:80
Answer
any FIVE questions
All
questions carry equal marks
-
- -
1.
(a) List the micro-operations required to carryout the following instructions. Assume
a simple CPU with single accumulator.
i. AND to accumulator ii. OR to accumulator iii. Jump
iv. Jump
if AC = 0.
(b) The ALU is a combinational circuit with no internal
storage. Justify this. [12+4]
2. (a)
Explain the following terms:
i. Micro program
ii. Microinstruction
iii. Microprogramming
iv. Microprogramming language.
(b) Draw the diagram of micro
architecture control unit and explain. [8+8]
3. What
are the different mapping techniques
of cache memory? Describe
each technique with a suitable diagram. [16]
4. (a)
What do you mean by virtual memory?
(b) Explain the demand paging technique in detail. [8+8]
5.
(a) What is the purpose
of I/O interface? Explain
the Communication link between
the processors I/O bus and peripheral devices.
(b) Describe different commands that an I/O can receive from CPU. [8+8]
6.
(a) A DMA controller transfers 16-bit words to memory using cycle
stealing. The words are assembled from a device that transmits characters at a rate of 2400 characters per second. The CPU is
fetching and executing instructions
at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
(b) What are Bus arbitration schemes? Explain.
[8+8]
7. (a)
Distinguish between basic bus configuration and P C I configuration.
(b) Perform the arithmetic operations
35 + 40and - 35 + (- 40) with binary numbers
in singed 2’s complement representation and signed- magnitude representation.[8+8]
8. Explain the following branch instructions of a hypothetical computer:
(a) BRP X
(b) BRN X (c) BRZ X
(d) BRO X. [4+4+4+4]
*****
Code.No: NR/RR310201
NR/RR
SET-3
JAWAHARLAL
NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD III B.TECH I-SEM SUPPLEMENTARY
EXAMINATIONS JUNE - 2010
COMPUTER ORGANIZATION (Common to EEE, ECE, EIE & ETM)
Time:
3hours
Max.Marks:80
Answer
any FIVE questions
All
questions carry equal marks
-
- -
1. What
are the different mapping techniques
of cache memory? Describe
each technique with a suitable diagram.
[16]
2. (a) What do you mean by virtual memory?
(b) Explain the demand paging technique in detail. [8+8]
3.
(a) What is the purpose
of I/O interface? Explain
the Communication link between
the processors I/O bus and peripheral devices.
(b) Describe different commands that an I/O can receive from CPU. [8+8]
4. (a) A DMA controller transfers 16-bit words
to memory using cycle
stealing. The words are assembled from a device that transmits characters at a rate of 2400 characters per second. The CPU is
fetching and executing instructions
at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
(b) What are Bus arbitration schemes? Explain.
[8+8]
5. (a) Distinguish between basic bus configuration and P C I configuration.
(b) Perform the arithmetic operations
35 + 40and - 35 + (- 40) with binary numbers
in singed 2’s complement representation and signed- magnitude representation.[8+8]
6. Explain the following branch instructions of a hypothetical computer:
(a) BRP X
(b) BRN X (c) BRZ X
(d) BRO X.
[4+4+4+4]
7.
(a) List the micro-operations required to carryout the following instructions. Assume
a simple CPU with single accumulator.
i. AND to accumulator ii. OR to accumulator iii. Jump
iv. Jump
if AC = 0.
(b) The ALU is a combinational circuit with no internal
storage. Justify this. [12+4]
8.
(a) Explain the following terms:
i. Micro program
ii. Microinstruction
iii. Microprogramming
iv. Microprogramming language.
(b) Draw the diagram of micro
architecture control unit and explain.
[8+8]
*****
Code.No: NR/RR310201
NR/RR
SET-4
JAWAHARLAL
NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD III B.TECH I-SEM SUPPLEMENTARY
EXAMINATIONS JUNE - 2010
COMPUTER ORGANIZATION (Common to EEE, ECE, EIE & ETM)
Time:
3hours Max.Marks:80
Answer
any FIVE questions
All
questions carry equal marks
-
- -
1.
(a) What is the purpose
of I/O interface? Explain
the Communication link between
the processors I/O bus and peripheral devices.
(b) Describe different commands that an I/O can receive from CPU. [8+8]
2.
(a) A DMA controller transfers 16-bit words to memory using cycle
stealing. The words are assembled from a device that transmits characters at a rate of 2400 characters per second. The CPU is
fetching and executing instructions
at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
(b) What are Bus arbitration schemes? Explain.
[8+8]
3. (a) Distinguish between basic bus configuration and P C I configuration.
(b) Perform the arithmetic operations
35 + 40and - 35 + (- 40) with binary numbers
in singed 2’s complement representation and signed- magnitude representation.[8+8]
4. Explain the following branch instructions of a hypothetical computer:
(a) BRP X
(b) BRN X (c) BRZ X
(d) BRO X.
[4+4+4+4]
5.
(a) List the micro-operations required to carryout the following instructions. Assume
a simple CPU with single accumulator.
i. AND to accumulator ii. OR to accumulator iii. Jump
iv. Jump
if AC = 0.
(b) The ALU is a combinational circuit with no internal
storage. Justify this. [12+4]
6. (a) Explain the following terms:
i. Micro program
ii. Microinstruction
iii. Microprogramming
iv. Microprogramming language.
(b) Draw the diagram of micro
architecture control unit and explain. [8+8]
7. What
are the different mapping techniques
of cache memory? Describe
each technique with a suitable diagram. [16]
8. (a)
What do you mean by virtual memory?
(b) Explain the demand paging technique in detail. [8+8]
*****
